1. Field of the Invention
The present invention relates to a method of forming semiconductor device, and more specifically, to a method of fabricating a metal oxide semiconductor field effect transistor (MOSFET) with raised extended source and drain structure for used in deep sub-micron meter range.
2. Description of the Prior Art
The semiconductor industry has been advanced in an ever brisk pace, recently. In order to achieve high performance integrated circuits or high package density of a wafer, the sizes of semiconductor devices have become smaller and smaller than before in the field of Ultra Large Scale Integrated (ULSI) technologies. The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the metal-oxide-semiconductor transistor also follows the trend. As the size of the devices is scaled down, silicon based nano-scale electronics have been attention for these years. Integrated circuits includes more than millions devices in a specific area of a wafer and electrically connecting structure for connecting these devices to perform desired function. One of the typical devices is metal oxide semiconductor field effect transistor (MOSFET). The MOSFET has been widely, traditionally applied in the semiconductor technologies. As the trend of the integrated circuits, the fabrication of the MOSFET also meets various issues to fabricate them. The typically issue that relates to hot carriers injection is overcame by the development of lightly doped drain (LDD) structure.
Further, the requirement of the devices towards high operation speed and low operation power. For deep sub-micron meter MOS devices, the self-aligned silicide (SALICIDE) contact, ultra-shallow source and drain junction are used for improving the operation speed and short channel effect. In the prior research, the CoSi2, NiSi have been used for deep sub-micron high speed CMOS due to the low sheet resistance of fine silicide line. However, it is difficult to make ultra-shallow junction and form SALICIDE contact without degrading the device performance.
The requirement of the ULSI CMOS technology is the need of devices operated at low supply voltage and they have high speed. When the supply-voltage is-reduced, the threshold voltage needs to be scaled down to achieve the desired circuit switching speed. IBM has proposed that CMOS employs non-uniform channel doping profiles and ultra-shallow source and drain extensions and halos, which can be referenced in “CMOS technology scaling 0.1 μm and beyond, IBM semiconductor research and development center, Bijan Davari, 1996, IEDM, 96-555”. For the high performance case, the threshold voltage is scaled down less than the supply voltage in order to maintain a reasonable standby current.
Please refer to FIG. 1, it shows prior source and drain structure. As illustrates in the FIG. 1, a gate 4a is formed over a substrate 2a. The side wall of the gate is surrounded by a dielectric layer 8a, and side wall spacers 6a formed thereon. Source/drain 10a is in the substrate 2a and the source/drain extension 15a is adjacent to the source/drain 10a. Silicide layer 12a is formed on the exposed silicon surface. Once the source/drain extension becomes shallower, the distance between Co-silicide and ultra shallow junction becomes shorter. Then, the junction leakage (the dash line area 14) or punch through issue is enhanced. As the extended source and drain junction becomes shallower, the distance between source and drain silicide and junction becomes shorter. This causes the current leakage issue from the ultra shallow junction area. One of the method is to form the raised source and drain structure. However, as the devices become smaller and smaller, the interfacial stress between silicide and source/drain area becomes more and more serious.
U.S. Pat. No. 6,165,903 which assigned to Advanced Micro Devices, the prior art includes to form metal silicide on the gate and source/drain junction. A silicon layer is formed on substrate to react with the metal silicide, thereby forming raised metal silicide on the source/drain region. The deposited silicon is a source of silicon that is employed as a diffusion species during the transformation of the high resistivity metal silicide to a low resistivity metal silicide. However, the tremendous stress of the epitaxy silicide layer formed by metal and silicon substrate generates defect under source/drain regions for sub-0.1 micron meter technology.
U.S. Pat. No. 4,998,150 which assigned to Texas Instruments Incorporated, entitled ‘Raised source/drain transistor’. In the structure, a raised source/drain transistor is provided having thin sidewall spacing insulators adjacent the transistor gate. A first sidewall spacer is disposed adjacent thin sidewall spacing insulator and raised source/drain region. A second sidewall spacer is formed at the interface between field insulating region and raised source/drain region. One of the aspects of the present invention includes the formation of a raised source/drain transistor that accommodates controlled doping of ultra-shallow junctions subsequent to the deposition of the raised regions. In comparison to prior processes, this aspect of the present invention prevents uncontrolled movement of previously implanted dopants during the process of depositing the raised source/drain region. Further, U.S. Pat. Nos. 5,677,214 and 6,218,711 describe a selective raised source/drain. If the raised source/drain epitaxy layer followed by metal silicide formed on the top of the raised source/drain area thus impacts the sub-0.1 micron meter performance. If the raised source/drain area is polycrystalline, the remained polycrystalline Si layer below the metal silicide layer should reduce the electron/hole mobility of the device.